The present invention relates to methods and apparatus for testing digital systems including integrated circuits and, more specifically, to built-in self testing of integrated circuits having multiple clock domains with asynchronous clocks and non-integer frequency ratios.
Testing of digital systems, such as the core logic of an integrated circuit, is typically performed by loading a test pattern or stimulus into scannable memory elements in the system, launching the test data into the system, operating the system in normal mode for one clock cycle of the system clock, capturing the response of the system to the test stimulus, unloading the test response from the system and then comparing the response to the response which should have been obtained if the system was operating according to design. This test procedure is satisfactory for relatively simple systems which are comprised of only one clock domain or a plurality of clock domains whose clock are derived from the same clock source. It is well established that, in order to obtain accurate results, the test must be performed while operating the memory elements in the various clock domains at their respective normal operational clock rates during the capture operation. Difficulties arise when clock domains have clock sources which are different from the test clock signal used to perform the test, when domains have different clock rates, and/or when signals cross the boundary between clock domains having different clock frequencies. Since the elements in one domain operate at a different frequency from that of other domains in the system, special provisions must be made during testing to ensure that signals traversing clock domains are synchronized. Otherwise, the test response from the system will not be repeatable and test results will be unreliable. The problem is especially severe in built-in self-test systems.
Methods have been developed for testing systems in which the ratio of the frequencies of two clock domains is an integer. However, it is not uncommon for digital systems to employ asynchronous clocks whose frequencies are not multiples of each other. For example, one clock domain could employ a clock rate of 200 MHz and other domain could employ a clock rate of 78 MHz, resulting in a non-integer frequency ratio of 2.564 . . . Solutions have yet to be developed for clock domains having non-integer frequency ratios. Testing of such systems using the functional system clocks is difficult because the phase relationship between the system clocks is not known and is variable over time. The term xe2x80x9cfunctional system clockxe2x80x9d refers to the normal operating frequency of a digital system or portion thereof. In order to achieve very high reliability circuits, it is essential that all clock domains be tested at full-speed.
Heretofore, such circuits have been tested by using test clock rates that are essentially the same as the functional clock rates but disabling all signal paths crossing clock domain boundaries and repeating the test for each clock domain. The primary drawbacks of this approach are that part of the logic is not tested and a series of tests must be performed in order to test all parts of the system. However, even then, it is not possible to obtain results for all parts of the system operating concurrently at speed.
It is also known to use test clock rates that are as close as possible to those of the functional clocks without exceeding the functional clock rates and that are multiples of each other. This is done by using the fastest functional clock as the test clock for the domain with the fastest clock rate and generating the test clocks required by other clock domains from the main test clock signal using a simple clock divider. For example, in a system having one clock domain with a functional clock frequency of 200 MHz and another clock domain with a clock frequency of 78 MHz, test clock rates of 200 MHz and 50 MHz would be used for testing. Nadeau-Dostie et al U.S. Pat. No. 5,349,587 granted on Sep. 20, 1994 for xe2x80x9cMultiple Clock Rate Test Apparatus for Testing Digital Systemsxe2x80x9d and Bhawmik U.S. Pat. No 5,680,543 granted on Oct. 21, 1997 for xe2x80x9cMethod and Apparatus for Built-In Self-Test With Multiple Clock Circuitsxe2x80x9d, both incorporated herein by reference, illustrate the latter approach. Clearly, the primary drawback of this approach is that one of the clock domains is not tested at its full-speed (78 MHz).
It is also possible to combine the above methods sequentially. The drawbacks of this approach are longer test times, more complex test circuitry than is desirable and the inability of simultaneously or concurrently testing all components at their functional clock rates.
Thus, there is a need for testing method and circuitry which enables the testing at the design or functional speed of digital systems having two or more clock domains with asynchronous clocks whose frequencies are not multiples of one another.
The present invention seeks to provide a method and a test control circuit for use in testing digital systems having core logic and scanable memory elements arranged in two or more clock domains with independent clock sources and, more specifically, for testing the entire circuit in a single session even if the clock frequencies are asynchronous.
Generally, the method of the present invention involves concurrently clocking a test stimulus into each scan chain of each clock domain using a clock frequency corresponding to or derived from a main test clock signal. In synchronous clock domains, in which the domain clock signal is synchronous with respect to the main test clock rate, the entire test stimulus is clocked in at the same respective clock rate. In asynchronous clock domains, in which the domain clock signal is asynchronous with respect to the main test clock rate, a portion of the test stimulus is clocked in using a first shift clock signal derived from the main test clock signal and the balance of the test stimulus is clocked in using a second shift clock signal which is derived from the respective domain test clock signal. Each domain is operated for one cycle of its respective domain test clock rate during the capture operation. Response data is clocked out of each domain using the clock signal used to clock in the test stimulus. In asynchronous clock domains, the first shift clock signal is used to clock out the response data.
The number of bits of the test stimulus clocked in at the respective first and second shift clock rates depends on whether the memory elements in the scan chain source a single cycle path or a multi-cycle path. In single cycle path scan chains, only the last bit is clocked in at the second shift clock rate. In multi-cycle signal path scan chains, the last few bits of the test stimulus are clock in at the second shift clock rate wherein the number of bits correspond to the number of cycles of the multi-cycle signal path. One aspect of the method resides in the timing of and the manner in which the transition from the first to the second shift clock is effected.
The test control circuitry is comprised of a main test controller which is clocked by a main test clock and an auxiliary test controller for each asynchronous clock domain. The auxiliary test controller is clocked by the main test clock and a domain test clock. The portion of the auxiliary test controller clocked by the domain test clock is very small and can operate at very high speed. This is particularly useful when the frequency of the domain test clock does not allow operation of a full test controller or when the clock domain itself contains a small amount of logic. The auxiliary test controller is provided with the capability of selecting between a first shift clock corresponding to or derived from the main test clock and a second shift clock corresponding to the domain test clock and operates to generate a memory element clock signal and re-timed configuration signals. The clock domains may be non-interacting, interacting, and/or the source of multi-cycle signal paths.
Thus, one aspect of the present invention is generally defined as a method of testing a circuit having two or more clock domains at respective domain test clock rates and under control of a main test clock signal, said circuit having core logic, a plurality of scannable memory elements, each having a clock input, an input connected to an output of said core logic and/or an output connected to an input to said core logic, and configurable in scan mode in which said memory elements are connected to define one or more scan chains in each said domain and in normal mode in which said memory elements are connected to said core logic in normal operational mode, said method comprising:
configuring said memory elements in scan mode;
concurrently clocking a test stimulus into each scan chain of each said clock domain including, for each clock domain having a domain test clock signal which is synchronous with respect to said main test clock signal, clocking said test stimulus at a shift clock rate derived from said main test clock signal and, for each clock domain having a domain test clock signal which is asynchronous with respect to said main test clock signal, clocking all but a predetermined number of bits of said test stimulus at a first domain shift clock rate derived from said main test clock signal followed by clocking said predetermined number of bits of said test stimulus at a second domain shift clock rate corresponding to said domain test clock rate;
configuring said memory elements of each scan chain in normal mode in which the memory elements of each scan chain are interconnected by said core logic in the normal operational mode;
clocking each memory element in each scan chain at its respective domain test clock rate for at least one clock cycle thereof;
configuring said memory elements in scan mode; and
clocking a test response pattern out of each of the scan chains at its respective domain shift clock rate during a respective scan-out interval, all respective scan-out intervals overlapping in time for a plurality of clock cycles at the highest of the respective clock rates.
Another aspect of the present invention is generally defined as a test controller for use in testing an integrated circuit having core logic circuitry and two or more clock domains operable at respective domain clock rates, each clock domain having a plurality of scannable memory elements, each having a clock input, an input connected to an output of said core logic and/or an output connected to an input to said core logic, and configurable in scan mode in which said memory elements are connected to define one or more scan chains in each said domain and in normal mode in which said memory elements are connected to said core logic in normal operational mode, said test controller comprising:
a primary test controller for controlling circuit test operations under control of a main test clock signal, said primary test controller being operable to:
concurrently load a test stimulus to each scan chain in each clock domain and receive response data from each said scan chain at respective domain shift clock rates;
generate respective domain shift clock signals derived from said main test clock signal for each clock domain; and
generate respective domain configuration control signal for each asynchronous clock domain in which the domain test clock signal is asynchronous with respect to said main test clock signal; and
an auxiliary test controller associated with each said asynchronous clock domain for controlling test operations therein under control of said primary test controller, each said auxiliary test controller being operable to generate a memory element clock signal derived from said respective domain shift clock signal when said respective domain configuration control signal is active and derived from said domain test clock signal when said domain configuration control signal is inactive;
each said auxiliary test controller being responsive to said respective configuration control signal by generating memory element configuration signals operable for configuring said memory elements in said scan mode or said normal mode.